module tb_multi # (parameter N=4)();
    reg G, reset, clk;
    reg [N-1:0] bus_in;
    wire [N-1:0] out;
    
    multi dut(G, reset, clk, bus_in, out);
    always
    begin
        clk=1; #5; clk=0; #5;
    end

    initial begin
        $dumpfile("tb_multiplicador2");
        $dumpvars;
        reset=1;G=0;#11;reset=0;bus_in=3;G=1;#20;G=0;#10;bus_in=10;G=1;#10;G=0;#10;#10;#10;#10;#1;#100;
        $finish;
    end
endmodule
module multi#(parameter N = 4)(G,reset,clk,bus_in,out);
    input G, reset, clk;
    input [N-1:0] bus_in;
    output [N-1:0] out;

    wire [2:0] Csignal;
    wire Z, q;
    wire [1:0] n_contador;
    wire [N-1:0] q_Q;
    wire shift_Q, Q_sout;
    reg shift;
    wire [N-1:0] q_B ;
    wire [N-1:0] pa_out;
    wire carry;
    reg load_Q;
    reg load_B;
    reg load_A;
    wire A_sout;
    reg reset_A;
    wire [N-1:0] q_A;
    reg load_C;
    wire C_sout;
    reg reset_C;
    wire q_C;
    reg enable_counter;
    reg load_counter;
    cu c(Q_sout, Z, G, reset, clk, Csignal);
    zero_detect zd(n_contador,Z);
    shiftreg # ((N)) Q(shift, load_Q, bus_in, A_sout, clk, Q_sout, q_Q, reset);
    register # ((N)) B(bus_in, load_B, q_B, clk, reset);
    ParallelAdder # ((N)) pa(q_A, q_B,0, pa_out, carry);
    shiftreg # ((N)) A(shift, load_A, pa_out, C_sout, clk, A_sout, q_A, reset_A);
    shiftreg # (1) C(shift, load_C, carry, 0, clk, C_sout, q_C, reset_C);
    counter #(2) coun(load_counter, enable_counter, clk, n_contador);

    //assign q=q_A[0];
    //assign shift = Csignal[2];
    //assign enable_counter = Csignal[2];
    //assign load_A = Csignal[2] &  Csignal[0];
    //assign load_C = Csignal[2] &  Csignal[0];
    always @ (*)
    begin
            load_B = Csignal==3'b001 ? 1 : 0;
            load_counter = Csignal==3'b001 ? 1 : 0;
            reset_A = Csignal==3'b011 ? 1 : 0;
            reset_C = Csignal==3'b011 ? 1 : 0;
            load_Q = Csignal==3'b011 ? 1 : 0;
            load_A = Csignal==3'b010 ? 1 : 0;
            load_C = Csignal==3'b010 ? 1 : 0;
            shift = Csignal==3'b110 ? 1 : 0;
            enable_counter = Csignal==3'b110 ? 1 : 0;
    end
endmodule
